Register Map

This page specifies the required software-accessible hardware control registers and the control interface.

Each project has an XML configuration file that specifies the modules that it uses, and each module has a configuration file that specifies the registers that it provides. The register system (specifically, the nf_register_gen.pl script) reads a project's configuration file to identify the modules (and number of instances of each module), reads the individual module configuration files, allocates memory in the register address space to each module instance and its registers, and finally outputs Verilog, C, and Perl files with the register allocation.

The automatically-generated outputs files include:

• Verilog (Hardware): $NF_DESIGN_DIR/include/registers.v
• C (Software): $NF_DESIGN_DIR/lib/C/reg_defines_<project-name>.h
• Perl (software): $NF_DESIGN_DIR/lib/Perl5/reg_defines_<project-name>.pm

Note: These files will not exist until after you build or compile your hardware project. (The generator script is invoked automatically as part of the build process).

For further information on the format of the XML files that specify register configuration, refer to the following documents at the NetFPGA project site:

• NetFPGA: Developer's Guide
• NetFPGA: Register System

For information on how the register chain works, view the Register Interface page.

As an example on how to instantiate registers in a NetFPGA-compliant format,the official XML files for both the switch and router projects have been posted below.  You should incorporate these elements into your own design. To do so, download the desired XML file and save it to the include/ directory in your project. Then, edit the include/project.xml file inside your current project.  Locate the block labeled <nf:group name="udp">, and then add a new entry to that block corresponding to the correct XML file.

Note: If you have problems incorporating the XML files, it might be helpful to ensure that your project name is consistent with the XML file name, i.e. "ethernet_switch" and "ip_router"

Registers

Only a subset of the full registers in the NetFPGA platform are described here. For the full list of all possible registers in your current project, along with their specific memory addresses and/or bit positions, refer to the definition files listed above.

MAC Queue Registers

These are registers for the 4 MAC Rx and 4 MAC Tx queues. An X in the register name can be a value between 0 and 3.

These registers are present in the initial NIC design

Input Arbiter Registers

Module description: Round-robin input arbiter

The registers of the input arbiter can be very useful for debugging packet flow through the system.

These registers are present in the initial NIC design

Output Port Lookup Registers (for Ethernet switch)

These registers (except for the number of hits/misses) are accessed in the same way a table is accessed. (See Reading/Writing Tables)

Tip: To incorporate these registers into your Ethernet Switch project, you will need to incorporate the following XML code into your project: learning_cam_switch.xml

These registers need to be added in the Ethernet Switch project.

Output Port Lookup Registers (for IP Router)

These define registers for accessing the hardware ARP cache, the Routing Table, setting IP and MAC addresses, statistics, and more. See Tables in the Router for more details.

For sections marked as a Table, see the Reading/Writing Tables section for more details.

Tip: To incorporate these registers into your IP Router project, you will need to incorporate the following XML code into your project: cam_router.xml

These registers need to be added in the Ethernet Router project.

Output Queues Registers

Module description: SRAM-based output queue using round-robin removal.

For the output queue register names, X can be a number between 0 and 7, representing the 4 MAC and 4 CPU output queues.

These registers are present in the initial NIC design

DMA Registers

These registers show the current status of the DMA engine.

These registers are present in the initial NIC design

Control Bits

MAC Control Bits

These are the bits in MAC_GRP_X_CONTROL_REG, and are used to change the state of the MAC queues.

Tables in the Router

There are three tables in the Router: The ARP table, the Routing table, and the Destination IP filter table.

• The ARP table has the following data registers: ROUTER_OP_LUT_ARP_MAC_HI_REG, ROUTER_OP_LUT_ARP_MAC_LO_REG, and ROUTER_OP_LUT_ARP_NEXT_HOP_IP_REG. This table gives the MAC address of the next hop IP found in the Routing table.
• The Routing table has the following data registers: ROUTER_OP_LUT_RT_IP_REG, ROUTER_OP_LUT_RT_MASK_REG, ROUTER_OP_LUT_RT_NEXT_HOP_IP_REG, and ROUTER_OP_LUT_RT_OUTPUT_PORT_REG. The routing table does a LPM search to find the next hop's IP address and the output port on which a packet should be forwarded.
• WARNING: Entries should be ordered such that the longest subnet masks are at the lowest index into the table.
• The Destination IP filter table has the following data register: ROUTER_OP_LUT_DST_IP_FILTER_IP_REG. This table should have the IP addresses of the router's interfaces in addition to any IP that the router should forward to the CPU such as the PWOSPF multicast IP address.

Reading/Writing Tables

To read a table:

1. Write the index of the entry to read
2. Read the data

To write a table:

1. Write the data to be stored
2. Write the index of the entry to be written

The data can span multiple registers. The registers used to read and write data are the same for reads and writes, but the registers used to write the indices for reads and writes are different.

For example: to write an entry into the switch MAC table: index 3, MAC address aa:bb:cc:dd:ee:ff -> MAC port 2

1. Write ((0x10<<16) | 0xaabb) into SWITCH_OP_LUT_PORTS_MAC_HI_REG (see below for details)
2. Write 0xccddeeff into SWITCH_OP_LUT_MAC_LO_REG
3. Write 3 into SWITCH_OP_LUT_MAC_LUT_WR_ADDR_REG

To read an entry from the MAC table at index 4:

1. Write 4 into SWITCH_OP_LUT_MAC_LUT_RD_ADDR_REG
2. Read SWITCH_OP_LUT_PORTS_MAC_HI_REG and SWITCH_OP_LUT_MAC_LO_REG