The NetFPGA hardware files have two key components:
- A base library that contains the reference NIC implementation, and
- Your projects directory that contains custom verilog modules that override the base NetFPGA library (stored in your home directory)
Let's explore these two components in more detail:
The NetFPGA base library contains the following folders. You should not need to modify any files that are part of the base library.
- bin/ - Contains scripts for running simulations and setting up the environment, along with programs used by the NetFPGA development team at Stanford.
- lib/ - Contains stable modules and common parts that are needed for simulation, synthesis, and design.
- C/ - Common software and code for reference designs
- Makefiles/ - Makefiles for simulation and synthesis
- Java, python, Perl5/ - Common libraries to interact with reference designs and aid in simulation
- scripts/ - Scripts to initialize the board PCI core
- verilog/ - Verilog modules and files that make up the basic NetFPGA design
- projects/ - This folder is described next.
The projects/ directory shown above contains a basic example of a NetFPGA project (a NIC). Additional projects can also be created in this directory, allowing you to override and extend the basic NetFPGA functionality provided in the base library.
The provided projects/ directory contains the following folders:
- cpci - Code for the Spartan FPGA PCI controller. You will not modify this code, but it is compiled as part of the simulation process, and thus needs to be in your projects directory instead of the read-only library.
- driver - The software driver for the NetFPGA card
- selftest - The selftest for the NetFPGA hardware
- reference_nic/ - A sub-project that instantiates the basic NetFPGA design, which is a 4-port NIC. This directory contains no verilog code, because all NIC components are part of the standard library.
- doc/ - Contains documentation about this project
- include/ - Contains files that define macros and files that specify what library verilog modules should be included in the project for simulation and/or synthesis
- src/ - Contains all the custom verilog code to be used for synthesis and simulation
- sw/ - Contains all software parts for the project
- synth/ - Contains user .xco files to generate Xilinx cores, the Makefile to implement the design, and all Xilinx compiler-generated products.
- verif/ - Contains hardware simulator test files and simulator packet generator scripts
Any custom projects you create should follow the general format of the reference_nic project.