The group projects are worth a significant portion of the course grade. Students will be graded based on technical accomplishment, the quality of the written and oral presentations describing the projects, and teamwork. The point value for each project is given below, but these breakdowns are subject to change.
Each student will join a group for the duration of the semester. All projects are to be done by your assigned group. Each group may split up the project tasks in whatever way they see fit, as long as the overall course division of labor is equitable and documented in the written project reports. You may use any available reference material to help you with the projects. However, you must clearly identify any code that was not written by your group, state where it came from, and to what extent you modified it. You may discuss high-level approaches to the course projects with students in the class outside your group, but different groups may not share specific implementations or code. You may not consult solutions to the project from past semesters of this course or from similar courses at other universities. If you have access to materials relating to NetFPGA for your research or other activities, you must speak with the instructor before beginning any of the projects.
Projects are due at 11:59:59pm on the announced day. All submissions at midnight or after are considered late.
Each group has 3 slip days (24-hour extensions of a deadline) to be used as desired. These are "per-group", not "per-hardware-project" or "per-software-project". Email the instructors in advance of the deadline in order to use a slip day.
After all slip days have been exhausted, projects that are handed in late will lose 20% per day. As the projects are due at 11:59PM, this means that 20% will be deducted at midnight. An additional 20% will be deducted each midnight thereafter, until the project is submitted or the project grade reaches 0.
Partial credit will not be given for the functionality tests. Either a test passes or it does not. As tests for these projects can not be made orthogonal, this means that if the basic functionality does not work then most of the functionality points will be lost. For example, if your software router is unable to process ARP packets correctly, it will be difficult to receive any points at all. Similarly, if your hardware router is unable to calculate checksums correctly, it will be difficult to receive any points at all. It is important that you make sure that the basic functionality of the projects is absolutely correct before moving on to the more complicated functionality. Testing, especially regression testing, is also extremely important to ensure that as you add advanced features you do not break the basic functionality of your project.
- Project Groups
- Network Topology
- Register Interface and Register Map
- Verilog Hierarchy
- Project Submission
- Grading Rubrics
HW Project 1 - Learning Ethernet Switch (10%)
Design and implement a 4-port learning Ethernet switch by extending the design of a simple 4-port Ethernet NIC.
Description: Project - Learning Ethernet Switch
Checkpoint: Monday, Feb 14th, 2011 at 11am
- At the project checkpoint (held during the regular class period), you must demonstrate proper functioning of your switch in the simulator, such as packet forwarding and register access to the forwarding table. In addition, you should be able to provide and discuss a brief written plan for accomplishing the rest of the project (hardware operation, software, report) by the final deadline.
Final deadline: Wednesday, Feb 23rd, 2011 at 11:59pm (extended until Friday, Feb 25th, 2011 at 11:59pm)
HW Project 2 - Router Design Document (5%)
Create a hardware design document for a 4-port Ethernet IP Router detailing its feature set, architecture, implementation, and testing.
Description: Project - Router Design Document
Due: Monday, March 14th, 2011 at 11:59pm
HW Project 3 - Router Implementation (20%)
Implement a 4-port IP Router that uses a forwarding table based on longest prefix match lookup, and provide control registers accessible from the host system for future software integration.
Description: Project - Hardware IP Router
Due: Wednesday, April 20th, 2011 at 11:59pm
SW Project 1 - Router Implementation (20%)
Implement the main features of an IP router in software.
Description: Project - Software Router
Due: Friday, Mar 18th, 2011 at 11:59pm
SW Project 2 - User Interface (15%)
Add a user interface to your software IP router.
Description: Project - User Interface
For software-only groups: Wednesday, April 6th, 2011 at 11:59pm
For mixed hardware/software groups: Monday, April 18th, 2011 at 11:59pm
SW Project 3 - Dynamic Routing (20%)
For software-only groups: Implement a dynamic routing algorithm based on OSPF. Project is in liu of the Hardware IP Router project.
Description: Project - Dynamic Routing
Due: Monday, April 25th, 2011 at 11:59pm
Router Integration / Interoperability / Performance (15%)
Integrate the hardware IP Router with the corresponding software control systems and optimize the IP router for performance.
Description: Project - Integration
Due: Wednesday, May 4th, 2011 at 11:59pm
Final Report and Presentation (15%)
Description: Project - Final Report and Presentation
This project has been cancelled for the spring 2011 semester.